A high speed digital storage oscilloscope (DSO) architecture is depicted in U.S. Pat. No. 5,986,637 issued Nov. 16, 1999 to Etheridge et al. and incorporated herein by reference in its entirety. In this architecture, acquired data is stored in an acquisition memory and, upon occurrence of a trigger event, the stored data is aligned to the triggering event and processed by an acquisition rasterizer. The resulting raster data is stored in a display raster memory for subsequent display on a display device.
Because of the high processing power required to process the very high volume of data acquired by a DSO (or other test and measurement instruments), high performance oscilloscopes have traditionally used specialized custom integrated circuits to rasterize the waveform content. These integrated circuits often include the circuitry necessary to display a resultant image (i.e., a display controller) in addition to the rasterizing circuitry.
In one application, the rasterizer increases the intensity of (attacks) individual pixels with each new waveform and the display controller reduces the intensity of (decays) these pixels as they are moved to the screen. This scheme tends to emulate the characteristics of a traditional analog oscilloscope display (i.e., a cathode ray tube) where the brightness of a phosphor is increased by the display of new waveform content and reduced by the decay of the phosphor. In order to emulate the CRT, the display process needs to be at a constant rate with time.
While improving waveform throughput, the above architecture has several drawbacks. First, because the decay operation has been attached to the display process, this technique is unable to emulate the attack and decay characteristics of an analog CRT while achieving high waveform throughput. Each composite image represents a snapshot in time that is reset with each new raster/display cycle. Additionally, since modern high-speed oscilloscopes typically use multiple analog-to-digital converters feeding multiple memory controller (i.e., demux) parts, the high-speed rasterization takes place in multiple locations. In order to display these raster images, the images must be consolidated at a central location which, typically, comprises a specialized integrated circuit including display capabilities.
Finally, since there is still a strong desire to have a gray scale attack/display capability to emulate a traditional CRT display, these instruments have two display modes which reflect an undesirable modal behavior. In a first mode of operation, data is rasterized within the acquisition system and consolidated for display. In the second mode of operation, waveform data is moved to a central rasterizer that includes gray scale attack/display capability. Unfortunately, display update rates using these two modes of operation can differ by very large amounts.